This invention relates to testers for testing the performance of semiconductor devices such as memory IC chips, and more particularly to monitoring circuits thereof which display as two-dimensional images the waveforms of the test signals which are input to the semiconductor devices during a dynamic function test thereof.
Testers for semiconductor devices evaluate the performance of semiconductor devices such as memory IC's as follows: Test waveform signals are formed by means of a pattern generator, a timing generator, and a formatter, and are input to a semiconductor device to be tested. Then, the signals which are output in response thereto from the semiconductor devices under test are compared with the expected patterns so as to determine the performance of the semiconductor devices. FIG. 1 shows a block diagram illustrating conceptually the hardware organization of a typical tester for semiconductor devices.
In FIG. 1, a central processing unit (CPU) 1 controls the overall operation of the tester for semiconductor devices. A pattern generator 2 generates various pattern signals, such as test waveforms to be input to the semiconductor devices, and expectation patterns with which the outputs from the semiconductor devices are compared so as to determine whether the device under test (DUT) 6 is functioning well or not. On the other hand, a timing generator 3 generates various timing signals which determine the reference timing needed in the functional test of the device under test 6. Further, a formatter 4 composes the waveforms, generated by the pattern generator 2, and the reference timing determined by the timing generator 3, so as to form test waveforms to be input to the device under test 6. A pin electronics circuit 5, which constitutes an interface for the input and output pins of the device under test 6, comprises drivers (FIG. 2) and comparators (FIGS. 3 and 4) described hereinbelow.
The device under test 6 is a memory IC which comprises a number of pins for inputting and outputting signals thereto and therefrom. In general, most of the pins are input pins via which address or control signals are input to the device under test 6; the output pins from which data signals are output or input/output pins to and out of which data signals are input and output are few in number (generally one, four, or eight, according to the arrangement of the bits within the memory IC).
FIG. 2 is a block diagram which shows the principle of operation of a driver within the pin electronics 5. A driver 7 is provided for each one of the output pins of the tester (which are connected to respective input or input/output pins of the device under test 6). The driver 7 converts the digital test waveform signals generated by the formatter 4, into a waveform pattern in accordance with the voltage levels specified for the device under test 6, so as to apply a high quality waveform to the device under test 6.
On the other hand, FIG. 3 shows a block diagram showing the principle of operation of a comparator within the pin electronics 5. FIG. 4, on the other hand, shows the details thereof. A comparator is provided for each one of the input pins of the tester (connected to the respective output or input/output pins of the device under test 6). The comparator 8 compares the output signal of the device under test 6 with the high reference output voltage level VOH or low reference output voltage level VOL at each reference timing determined by a timing signal (strobe) from the timing generator 3, so as to determine whether the voltage levels and the timing of the output signal of the device under test 6 follow the expected value pattern. Namely, as shown in FIG. 4, the comparator 8 comprises a high comparator 8a and a low comparator 8b, and the circuit or means schematically shown by a block 9 determines, according to the expectation value signal, which, of the high comparator 8a or the low comparator 8b, is put into operation. The timings of the comparison is judgements are determined according to the strobe signal input to the circuit 9. The tester thus evaluates the functional performance of the device under test 6.
If, however, the test waveform input to the device under test 6 is itself deviated from the predetermined waveform pattern and timing, it becomes impossible to evaluate the functional performance of the device under test 6 with high precision. Thus, the output waveform of each one of the driver 7 of the pin electronics circuit be monitored and displayed. As a method of monitoring the output of the drivers 7, one may input the output waveforms of each one of the drivers 7 directly to a comparator. Thus, a tester having a test waveform monitoring function has been developed, wherein each one of the pins is provided with a driver 7 and a comparator 8, as shown in FIG. 5. In FIG. 5, the switch 10 is closed when the output waveform of the driver 7 is to be monitored, so that the output of the driver 7 is input to the comparator 8.
The last mentioned tester with all its pins provided with the input/output function, however, has the following disadvantage. Namely, as pointed out above, most of the pins of memory IC chips are provided exclusively for receiving input signals, and there is no need to provide a comparator for the output pins of the tester which are connected to the input pins of the device under test. In spite of this, each one of the pins of the above tester with the monitoring function is provided with a separate comparator, which makes the circuitry thereof complicated and makes the tester expensive.